This invention relates to CMOS/NMOS integrated circuits and more particularly to such circuits that realize logic functions with a combination of CMOS and NMOS devices such that circuit propagation delays remain constant despite variations in the supply voltage.
As one can ascertain, there are various classes of FET logic circuits that have been developed over the years. Once of the most widely employed is CMOS which employs the complementary symmetry of n-channel and p-channel units to allow a voltage swing from one transistor to the other with very low power dissipation per gate at standby. The propagation delay of these circuits is typically between 20 to 50 nano seconds. While CMOS devices have low quiescent power and good noise immunity, the logic packing density in CMOS devices is not as good as can be achieved by NMOS devices and certain other logic families. As one can ascertain, a large fan-out, for example, implies a larger load capacitance and thus a longer propagation delay.
The prior art was aware of this fact and there are references indicating the prior art which suggest the use of CMOS/NMOS integrated circuits to be used to fabricate digital integrated circuits. The article entitled "A CMOS Process for VLSI Instrumentation" by Tong Qin Yi and J. N. Robertson appeared in the Microelectronics Journal, Vol. 13, No. 6, 1982, pgs. 29-32. According to this article, a choice of CMOS/NMOS technology to implement the specified digital function depends upon the requirements of speed and packing density of the integrated circuit. In this manner, CMOS and NMOS devices are combined on the same integrated circuit chip and employ specific logic circuits using either only CMOS technology or only NMOS technology. Thus, the article discusses the fabrication of CMOS/NMOS integrated circuits and how CMOS devices are combined with NMOS devices on the same substrate to realize analog and digital circuits. The problem in conjunction with such approaches is that the propagation delay in a CMOS device, particularly in the CMOS inverter, determines the switching speed and cut-off frequency of the entire integrated circuit. This propagation delay, particularly for the CMOS inverter, is undesirably a function of the supply voltage. The prior art is well aware of this problem.
See an article entitled "Technology and Performance of Integrated Complementary MOS Circuits" by T. Kline in the Journal NEREM Record, 1967 on pgs. 168-169. As indicated, the article discusses the propagation delay in CMOS devices as a function of supply voltage. CMOS switching responses for example for 9 volts and 15 volts supply voltage are shown for comparison in FIG. 4.
This voltage dependence is an extremely troublesome problem especially when one desires to implement delay circuit elements as for example digital filters or ring oscillators whereby the propagation delay determines reliable circuit operation. Hence, by employing the CMOS inverter in such circuits one experiences great problems with power supply variation as affecting propagation delay.
It is therefore an object of the present invention to compensate for the voltage dependence of the propagation delay in combined circuits which employ CMOS/NMOS technology and which combined circuits are realized mainly by CMOS technology.
A "function" as used herein includes a subunit of the integrated circuit which, as will be explained, is implemented separately with a single, digital, basic circuit type. Such basic circuit types are for example the adder, the multiplier, the divider, the comparator, the memory, shift register, analog-to-digital converter, digital-to-analog converter, sample and hold cells as well as flip flops, inverters, and gates. Such circuits for example as adders, multipliers and so on are thus thought of being composed of separate cells. A gate as employed above means any logic circuit whose single output provides a signal depending upon the combination of signals at its input. For example, these can be AND, OR gates and so on.
For the purposes of the present invention an inverter is regarded as the simplest gates. The CMOS inverter employs a p-channel MOS transistor and an n-channel MOS transistor on the same substrate. The drain-source paths of the respective p- and n-channel transistors are connected in series with a junction thereof being an output and the respective gates are coupled or connected together. The drain-source paths are connected between the supply voltage and the reference voltage. During operation of the inverter, an input signal is applied to the gates causing one transistor to be held on while the other is held off. The output of the inverter is determined by the quiescent leakage current of the off transistor.
The concept employed with this invention is based upon the utilization within a function as described above of CMOS/NMOS circuits. Thus, in order to provide a constant propagation delay with power supply variation, a sub number p of the necessary basic circuits as CMOS circuits and a remaining sub number q enhancement mode NMOS circuits are employed. The NMOS circuits employ a current source, particularly a depletion mode transistor as a load device, for example, preferably as a depletion mode NMOS basic circuit. This approach completely departs from the above described prior art approach in which only entire functions are realized by either of the technologies referred to above but not utilizing a sub number p of CMOS basic circuits and a sub number q as enhancement mode NMOS basic circuits.
Thus, as one will ascertain, with the solution as described above, the oscillation frequency of ring oscillators for example can be made independent of the supply voltage without an additional voltage regulating circuit. Thus, the solution and circuits which are fabricated in accordance with this invention require no additional chip area which normally would be needed to accommodate a voltage regulating circuit. Such voltage regulating circuits for example have been shown in the prior art.
See for example European Pat. No. 0,219,291 filed on Oct. 6, 1986 entitled CMOS Integrated Circuit for Signal Delay by N. Tomisawa. This patent describes an integrated circuit using an odd number of CMOS gate circuits arranged in a row with a large current supply located in the end. The current supply keeps the supply voltage constant in order to stabilize the propagation delay of the CMOS devices.
See Japanese Patent No. 60-25323 entitled Semiconductor Integrated Circuit filed on July 22, 1983 for Y. Kitagawa. This discloses a CMOS inverter and an input stage connected to the gate thereof. The input stage is an n-channel depletion load inverter which provides the CMOS inverter with a threshold voltage that is independent of supply voltage.
It is an object of the present invention to provide logic circuits which employ both CMOS/NMOS integrated circuits utilizing a combination of CMOS and NMOS devices such that the propagation delays thereof remain constant despite variations in the supply voltage.